1. Field of the invention
The present invention relates to the field of MOS integrated amplifiers and more specifically to input buffers utilizing differential amplifiers.
2. Prior Art
Various input buffer amplifiers for buffering an input signal prior to coupling that signal to other circuitry are well known in the prior art. Some of these input buffer amplifiers are also termed as a level shifter, wherein input voltage levels are shifted to be compatible with voltage levels of the associated circuitry. For example, many input voltage levels are specified as being compatible with standard transistor-transistor-logic (TTL) logic levels, that is, a logic threshold of 1.4 volts with a margin of 0.6 volts about the threshold. A typical high logic level TTL signal can be as low as 2.0 volts (VIH parameter), while a low logic level TTL signal can be as high as 0.8 volts (VIL parameter). However, when this TTL level signal is to be used in conjunction with complementary metal oxide semiconductor (CMOS) circuitry, the input levels must be changed to be compatible with the CMOS circuit. Typical CMOS logic thresholds vary approximately from 2.0 to 3.0 volts, while the margin around the threshold can be substantially equal to the difference between the threshold and the supply rails. An input buffer functions to translate the TTL compatible levels of the inputs to the CMOS compatible levels for use with CMOS circuitry inside a CMOS chip. This CMOS chip also includes the input buffer on the chip.
In designing a built-in logic-threshold level translator in a prior art input buffer, the buffers are built to be sensitive to input levels which are above or below the typically-specified threshold margin of 0.6 volts. Prior art implementations of input buffers are characterized by complex connections of carefully sized devices for obtaining proper performance. However, problems encountered in achieving level translation in prior art input buffers result in high dependence of the DC input parameters VIL and VIH on variations in processing and temperature. Further, the complexity of most input buffer configurations results in circuits which are generally not of high speed. In order to obtain the requisite speed, the circuits must be increased in size, which generally is accompanied by an increase of power dissipation.